Integrated circuits fabricated in semiconductor substrates generally comprise millions of transistors for the processing of analog or digital signals. MOS transistors comprise heavily doped N or P type regions forming a source and a drain within an oppositely doped P or N type substrate or well, which may be biased by a body terminal. A thin layer of silicon dioxide SiO2, or else a stack of dielectric materials, covers the area between the source and drain. A gate is formed on top of the silicon dioxide layer to control a channel extending between the source and drain.
The properties of a transistor include different physical parameters, such as a gate oxide thickness, doping levels, the length and width of the gate, and the materials used to fabricate the transistor. With advances in technology, such properties are often modified to obtain faster operation, smaller transistor size, less power-consumption, etc. However, once the transistors are fabricated, these properties may differ from those expected, and undesired effects may also result, such as an increased parasitic capacitance due to a thinner insulating oxide between the gate and the semiconductor substrate.
Thus, before implementing a new prototype transistor in production integrated circuits, it may be first necessary to characterize its properties so that it may be accurately modeled in a component library for future use. To that effect, “test structures” are commonly used to characterize the properties of the transistor.
For illustrative purposes, FIG. 1 shows a semiconductor wafer 1 comprising a plurality of transistor test structures 2, each comprising a plurality of prototype transistors (not shown) electrically linked to test pads Pi. The properties of transistors within a test structure 2 are essentially identical, while they vary from one test structure to the next. To characterize these properties, the semiconductor wafer is placed in a test apparatus, where the transistors undergo direct current (DC) and alternating current (AC) electrical tests.
FIG. 2 is a circuit diagram showing in detail a typical test structure 2. The test structure 2 comprises a DC test structure 2-1 and an AC test structure 2-2. Test structure 2-1 comprises transistors TDC1, TDC2 . . . TDCM and pads P1, P2, P3, P4. Test structure 2-2 comprises transistors TAC1, TAC2 . . . TACN and pads P5, P6, P7. Transistors TAC and TDC are assumed to be identical and to have been fabricated by the same process steps.
Transistor TDC1 has a drain D linked to pad P1, a gate G linked to pad P2, a source S linked to pad P3, and a body B linked to pad P4. The other transistors TDC2-TDCM are not linked to the pads and form conformity transistors with respect to transistor TDC1. By conformity transistors, it is meant that such transistors are merely fabricated to ensure a good conformity of transistor TDC1 to the design specifications, because it is difficult to fabricate a single isolated transistor that meets the desired specifications. Indeed, many processing steps involved in the fabrication, such as photolithographic patterning, etching, or chemical mechanical polishing, are sensitive to pattern density and/or pattern proximity effects. Thus, the features (material thickness, critical dimensions) of an isolated transistor would be different from the features of a similar transistor having neighboring transistors. Many other transistors are therefore fabricated near the transistor of interest.
Transistors TAC1-TACN have their sources S and drains D interconnected and linked to pad P5, their gates G linked to pad P6, and their bodies B linked to pad P7. Since the source S and drain D of each transistor are short-circuited, each transistor is equivalent to a “MOS capacitor.” The number of interconnected transistors provided in the test structure 2-2 depends on the size of the transistor, and can vary from tens to thousands of transistors.
Such a test structure 2 has the drawback of occupying a large area on the substrate surface. In particular, the surface of the pads is currently on the order of 100×100 microns, with a minimum distance of 100 microns between two pads. The surface area and distance between pads cannot be easily reduced since the pads should be accessible to the probe tips of a probe card. Consequently, the pad size dictates the size of the test structures, and thus determines how many test structures can be provided on a semiconductor wafer. It may be desired to provide a DC and AC test structure that occupies a smaller area on a semiconductor wafer.